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1、中南林業(yè)科技大學(xué)課程設(shè)計(jì)報(bào)告設(shè)計(jì)名稱：EDA技術(shù)及應(yīng)用課程設(shè)計(jì)姓名：學(xué)號：專業(yè)班級：電子信息工程一班院（系）：計(jì)算機(jī)與信息工程學(xué)院設(shè)計(jì)時(shí)間：2010年1月7日星期五設(shè)計(jì)地點(diǎn)：中南林業(yè)科技大學(xué)電子信息樓指導(dǎo)教師評語：成績：簽名：年月日目錄一、題目…………………………………………………………二、任務(wù)與要求（老師完成）……………………………………三、實(shí)驗(yàn)儀器·········································四、課程設(shè)計(jì)原理分析及相關(guān)知識概······················1.分頻模塊··················

2、·········································2.秒模塊··················································3.分模塊·················································4.小時(shí)模塊和12小時(shí)、24小時(shí)切換模塊·······················5.動態(tài)數(shù)碼管掃描和整點(diǎn)報(bào)時(shí)模塊····························五、實(shí)驗(yàn)步驟……………………………………………………·1.文本編輯各子模塊程序····

3、··········································2.建立工作庫文件夾，輸入設(shè)計(jì)項(xiàng)目原理圖或VHDL代碼并存盤············3.將以上模塊生成元器件···············································4.建立新的工程,將各個(gè)模塊的元器件用原理圖連接，進(jìn)行編譯···············5.進(jìn)行波形仿真并畫出仿真圖···········································6.分配管腳，并畫出管教分配圖·····················

4、····················7.程序下載并執(zhí)行····················································六、體會與收獲·······································一、實(shí)驗(yàn)題目用EDA層次化設(shè)計(jì)方法，即VHDL文本描述和原理圖描述結(jié)合設(shè)計(jì)一個(gè)數(shù)字鐘。二、任務(wù)與要求1.數(shù)字顯示當(dāng)前的小時(shí)、分鐘、秒鐘，可以整點(diǎn)報(bào)時(shí)；2.可以切換為12小時(shí)計(jì)時(shí)顯示和24小時(shí)計(jì)時(shí)顯示；3.一個(gè)調(diào)節(jié)鍵，用于調(diào)節(jié)目標(biāo)數(shù)位的數(shù)字。對調(diào)節(jié)的內(nèi)容敏感，如調(diào)節(jié)分鐘或秒時(shí)，保持按下時(shí)自動計(jì)數(shù)，否則以脈沖

5、計(jì)數(shù)；4.一個(gè)功能鍵，用于切換不同狀態(tài)：計(jì)時(shí)、調(diào)時(shí)、調(diào)分、調(diào)秒、調(diào)小時(shí)制式。三、實(shí)驗(yàn)儀器PC機(jī)、QuartusII軟件、FPGA開發(fā)板一、課程設(shè)計(jì)原理分析及相關(guān)知識概述1分頻模塊CLK50M是開發(fā)板時(shí)鐘信號，先將時(shí)鐘信號進(jìn)行分頻，送出clk，2hz，作為計(jì)時(shí)信號，clk1為1khz，作為掃描顯示信號2秒模塊CLK是時(shí)鐘信號,RESET是復(fù)位信號,SETMIN為分鐘設(shè)置信號,ENMIN作為下一模塊分鐘設(shè)計(jì)的時(shí)鐘信號,DAOUT輸出信號最后接在動態(tài)譯管碼芯片上,得出實(shí)驗(yàn)要求的秒顯示：3分模塊CLK接秒模塊中的ENMIN信號,RESET同樣是復(fù)位信號,ENHO

6、UR作為下一模塊小時(shí)(12與24)的時(shí)鐘信號,DAOUT輸出信號最后接在動態(tài)譯碼管芯片上.得出實(shí)驗(yàn)要求得分鐘顯示：4.時(shí)模塊和12小時(shí)、24小時(shí)切換模塊系統(tǒng)需要一個(gè)模12、模24和一個(gè)二選一數(shù)據(jù)選擇器來實(shí)現(xiàn)12和24的切換，復(fù)位鍵無效后，模12和模24計(jì)數(shù)器同時(shí)計(jì)數(shù)，模12和模24由同一個(gè)分鐘的進(jìn)位作為輸入，由數(shù)據(jù)選擇器選擇模12或模24輸出，到數(shù)碼管顯示。5動態(tài)數(shù)碼管掃描模塊數(shù)碼管的動態(tài)掃描需要一個(gè)將八位的輸入轉(zhuǎn)化為四位的輸出，還有一個(gè)三位的輸出，用來作為動態(tài)數(shù)碼管選擇器的輸入。五、實(shí)驗(yàn)步驟1.各模塊程序：1）用文本輸入法實(shí)現(xiàn)信號分頻,程序如下:lib

7、raryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityfenpinisport(clk50M:instd_logic;clk1,clk:outstd_logic);end;architectureartoffenpinissignalclk_data:std_logic;signalclk_da:std_logic;beginprocess(clk50M)variablecount:integerrange0to49999;beginifclk50M'eventa

8、ndclk50M='1'thenifcount=49999thencount:=